Memory system comprising a plurality of memory controllers and method for synchronizing the same

ABSTRACT

The invention relates to a memory system which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by means of operational memory commands using logical memory sector numbers. The inventive system is characterized in that for any memory operation requested by the host system (HS) the memory controller (SCx) affected with respect to a range of logical memory sector numbers (SCx) takes over the bus for communication with the host system (HS) by means of arbitration.

The invention relates to a memory system that is configured with aplurality of memory controllers disposed in parallel on a clocked busand memory chips associated with the respective memory controllers, andthat communicates via the bus with a host system by means of operationalmemory commands using logical memory sector numbers.

The size of a memory system, connected to a host system, is limited bythe characteristics of the memory controller. These memory controllersare designed very simple for reasons of cost-effectiveness and theyusually have the following characteristics:

up to 100 connector pins because inexpensive standard housings are used,

up to 10 chip select signals for the selection of memory chips,

up to 16 Kbytes internal RAM memory.

Building larger systems with more than 10 memory chips requiresadditional external components, such as decoders, bus transceivers andpossibly also RAM memory. From patent application publication DE 102 27256.5, for example, a system is known, wherein the memory chips of alarger memory unit are connected to a controller via additionalcomponents. In patent document U.S. Pat. No. 6,397,314, a system ofmemory chips on a controller is described, wherein the controller has adouble-wide data bus in order to supply two memory chips with data inparallel. This necessitates a non-standard memory controller, whichrequires additional connector pins. Furthermore, this system cannot beapplied to still larger systems, since it is limited to twosimultaneously addressable memory chips.

The invention is based on the object of creating larger memory systemsthan can be implemented with only one standard memory controller, bycombining multiple standard memory controllers without the use ofadditional components, wherein the maximum size is limited only by thenumber of utilized memory controllers. In order to manage with thenumber of connector pins prescribed by standard housings, only a minimumnumber of connector pins must be required for the interconnection ofmultiple memory controllers.

This object is met according to the invention in such a way that thememory system is configured with a plurality of memory controllersdisposed in parallel on a clocked bus and memory chips associated withthe respective memory controllers, and communicates via the bus with ahost system by means of operational memory commands using logical memorysector numbers, in such a way that, when a memory operation is requestedby the host system, the memory controller affected with respect to arange of logical memory sector numbers takes over the bus forcommunication with the host system by means of arbitration.

Advantageous embodiments of the invention are described in thesubclaims.

In PC systems, digital cameras, or similar equipment, referred to hereas host system, a bus is used to access a memory system and operationalmemory commands are used to communicate with it. This bus may beimplemented as so-called PCMCIA interface, IDE interface, or the like.The various possible applications of the host systems call for ascalable memory. With the parallel connection of a plurality of memorycontrollers with their respective assigned memory chips in a number thatis maximally administratable by the controller, a scalable memory sizeis achieved by using always identical memory controllers, which does notrequire any additional components as long as the physical specificationof the bus is adhered to. The communication of the controllers with thehost system takes place by using standardized commands, whereby thememory is addressed using logical memory sector numbers. By means of anarbitration process, ranges of logical memory sector numbers areexclusively assigned to each memory controller. For host commands thataffect the respective logical memory sector numbers, the assigned memorycontroller takes over processing of the command. The arbitration processensures that all logical memory sector numbers are processed by one ofthe controllers in each case and that when a command is given, e.g., aread command for a memory range of multiple sector numbers, thecontrollers appropriately complement each other and take over the bus atthe proper point in time.

Since there are a plurality of memory controllers that communicate withthe host system, one of the memory controllers will advantageously bedesignated on the bus as the master. It carries out the communicationwith the host system as long as no other memory controller takes overthe communication on the bus pursuant to the assigned memory sectornumber. More particularly, the master performs and responds to memoryoperations that affect the memory system as a whole. Memory operationsof this type are, for example, “Reset”, “Initialize”, “SetFeatures”,Diagnose”. In the case of some memory operations the commands areperformed by all memory controllers, the communication regarding thestatus, however, is conducted with the host system only by the master.

A significant advantage of the inventive implementation of the memorysystem is the use of only one line for arbitrating the bus between thememory controllers. This line is implemented as a tri-state line and hasthe three electric states “0”, “1”, “tri-state”. The state “0” may then,for example, be assigned to the logical “reserved” of the bus and thestate “1 ” to the logical “released”. During initialization of thecontrollers, the controllers receive numbers that also establish theassigned range of logical memory sector numbers. For example, in thecase of four controllers, controller 1 is assigned to memory sectornumbers 0,4,8,12, . . . , controller 2 to memory sector numbers1,5,9,13, . . . , controller 3 to memory sector numbers 2,6,10,14, . . ., controller 4 to memory sector numbers 3,7,11,15, . . . If, through aread command, sectors 4-11 are now to be read, controller 1 first takesover the bus for memory sector 4 by pulling the tri-state line to “0”.When the memory sector 4 has been transmitted, the controller releasesthe bus by switching the tri-state line to “1” or to “tri-state”.Controller 2 subsequently takes over the bus for memory sector 5 in thesame manner. In this manner the bus is continually taken oversuccessively by the controllers until all requested memory sectors, inthis case through sector 11, have been transmitted.

In order to achieve a clean switch of the control over the bus betweenthe controllers, a shield time is advantageously maintained during whichthe tri-state line is driven in a defined manner to “released”. The timeconstant of the tri-state line with a pull-up resistor is not shortenough during a fast bus operation. An advantageous shield time is onelength of a clock cycle on the bus.

As described above, the memory controllers are advantageously assignedto logical memory sector numbers in such a way that successive memorysector numbers have different controllers assigned to them. In thismanner as many logical memory sectors can be written or read quasi inparallel as memory controllers are available. In this manner, a highoperating speed of the memory system is achieved.

A particularly advantageous implementation of the memory system resultswhen flash memories are used as the memory chips. With this type ofmemory, long write and erase times occur as compared to read times. Dueto the interleaving of the operation of continuous logical memory sectornumbers by different memory controllers and, therefore, also differentmemory chips, these write and erase processes occur quasi in parallel,which increases the speed of the overall memory system. The real memorysectors, also referred to as “pages”, that are written into the flashchips may be several times the size of the logical memory sectors.

A simple and cost-effective memory configuration results when the memorycontrollers are integrated together on a semiconductor substrate. Withthis type of configuration, the costs for the individual housings areeliminated, and the number of connector pins between them is of noimportance. More particularly, additional control registers are thenalso provided on the semiconductor substrate, whereby, for example, thesequence of the individual memory controllers on the bus is establishedand the master is designated.

If such control registers do not exist, the designation of the masterand establishing of the sequence of the memory controllers on the bus isestablished during initialization of the memory system by means of thefollowing method:

The initializing host system knows the size of the memory system andnumber of utilized memory controllers. The tri-state line is in the“released” state. The host system sends, over the bus, a designationcommand that is recorded by all connected memory controllers. The memorycontrollers determine a wait time based on a counter that counts theapplied clock cycle. The memory controller whose wait time ends first,pulls the tri-state line to “reserved” for a specified length of time.It now has the memory controller number 1 and is also designated as themaster. The other memory controllers register this process. The mastersends to the host system a confirmation signal. In response, the hostsystem repeats the designation command. The master now withdraws fromthe designation procedure. All other memory controllers again waitaccording to their internally set wait time. The memory controller thatnow has the shortest wait time again occupies the tri-state line and,accordingly, is assigned the next memory controller number. The masteragain confirms the process to the host system. The memory controllerthat has now received a controller number also withdraws from theassignment process. The host system repeats the process with thedesignation command as often as corresponds to the number of memorycontrollers. If the host system receives no confirmation following adesignation command because a controller number was issued in duplicatedue to identical wait times, it repeats the entire process from thebeginning.

The wait time during the designation process is advantageously derivedfrom a counter in the memory controller by means of a randomly setcounter reading. The cycle that is incremented in this case is generatedseparately in each memory controller by means of a RC oscillator which,due to component tolerances in each case, does not run synchronouslywith the others. The likelihood of identical wait times, even in thecase of an identical random number for the counter reading, is thereforeextremely small.

After the designation of the controller numbers, a so-called anchorsector is written into each memory controller, which then contains theinformation regarding the memory size according to the total number oflogical sector numbers, the number of controllers, and the page size.With that, the memory controller has all necessary information toparticipate in the communication over the bus.

The embodiment of the invention is described in the figures by way ofexample.

FIG. 1 shows a block diagram of the memory system.

FIG. 2 shows the supplemented block diagram with integration of thememory controllers on a semiconductor substrate,

FIG. 3 shows a block diagram for the designation process of the memorycontroller numbers,

FIG. 4 shows a flow chart for the designation process of the memorycontroller numbers.

In FIG. 1, the host system HS communicates over the bus B with thememory controllers SCx. The x stands for the consecutive numbers 1through 4. The memory controllers SCx are connected in parallel on thebus B. Each memory controller SCx controls memory chips Fx, which arepreferably implemented in flash technology. In addition to the bus B,the memory controllers SCx are also connected to the arbitration lineBA, which indicates the respective state “reserved” or “released”. Theline BA is implemented as a tri-state line with pull-up resistor. Thefirst memory controller SC1 is, at the same time, designated as themaster M.

FIG. 2 shows the same block diagram as FIG. 1, without the memory chipsFx. The memory controllers SCx are integrated here on the semiconductorsubstrate H. Additionally provided on the semiconductor substrate H isthe control register KR, which contains for each memory controller SCx afield that contains the controller number Sx and the designation of themaster M. These values are written into the control register KR duringinitialization of the memory system.

In FIG. 3 the components for the designation process of the memorycontroller numbers are illustrated in a block diagram. The evaluationlogic AL in the respective memory controllers SCx monitors the commandsfrom the host system HS that are transmitted over the bus B. Because ofthe pull-up resistance RP the idle state of the line BA equals “1”.

Each memory controller SCx has a clock oscillator OSZ, whose frequencyis determined by the capacitor Cx and the resistor Rx. The cycle that isgenerated here is incremented in the counter Z until the counter readinghas reached the value W prescribed by the evaluation logic AL. As soonas this value is reached, the transistor T is switched through and thearbitration line BA is pulled to “0”.

The evaluation logic AL is also connected to the arbitration line BA andmonitors the same regarding whether another memory controller SCx haspreviously driven the bus to “0”.

FIG. 4 is an illustration of the sequence of the designation of thecontroller numbers Sx. First the host system sends a reset command,which sets the repeat counter N to 0 in the connected controllers SCx.Afterwards the host system sends the designation command to the memorycontrollers SCx. They have been waiting for the command and incrementthe repeat counter by 1. They start the counter Z. During the wait forthe counter reading to reach the random value W, the controller monitorsthe arbitration line BA. If the line BA takes on the state “0”, anothermemory controller SCx has determined its controller number Sx and thiscontroller returns to the wait mode. If the counter reading Z reachesthe value W, this controller drives the arbitration line to “0” for aspecified length of time and thus indicates that it has determined itscontroller number Sx. The controller number Sx corresponds to the valueof the repeat counter N. The host system HS is sent a confirmation ofthe recording of controller number Sx.

The host system HS monitors the bus B for a transmission confirmation.If no confirmation is received within a specified time limit, the hostsystem restarts the designation process from the beginning. If theconfirmation is received within the specified time, the host systemregisters this process.

When the repeat counter N has reached the maximum value MAXcorresponding to the number of specified memory controllers, thedesignation process is concluded. Otherwise additional designationcommands will be sent.

LIST OF REFERENCE NUMERALS

AL Evaluation logic

B Bus

BA Arbitration line for the bus

Cx Capacitor on the oscillator x

Fx Memory chips

H Semiconductor substrate

HS Host system

KR Control register

M Master

Max Maximum number of memory controllers

N Number of repetitions of the designation command

OSZ Oscillator

RP Pull-up resistor

Rx Resistor on the oscillator x

Sx Controller numbers

SCx Memory controller

T Transistor

W Random number

x 1 . . . 4, consecutive number

Z Counter

= Comparator

1. A memory system that is configured with a plurality of memorycontrollers (SCx) disposed in parallel on a clocked bus (B) and memorychips (Fx) associated with the respective memory controllers (SCx), andthat communicates via the bus (B) with a host system (HS) by means ofoperational memory commands using logical memory sector numbers,characterized in that in the case of a memory operation requested by thehost system (HS), the memory controller (SCx) affected with respect to arange of logical memory sector numbers takes over the bus for thecommunication with the host system (HS) by means of arbitration.
 2. Amemory system according to claim 1, characterized in that one of theparallel memory controllers (SCx) is designated as the master (M) on thebus (B) and that it performs the communication with the host system (HS)as long as none of the other memory controllers (SCx) has taken over thebus (B).
 3. A memory system according to claim 1, characterized in thatthe arbitration of the bus (B) between the memory controllers (SCx)takes place based on the addressed memory sector number and over asingle tri-state line (BA) that indicates the reservation of the bus (B)by the affected memory controller (SCx) during the communication periodwith a “reserved” signal.
 4. A memory system according to claim 3,characterized in that when the bus (B) is released by a memorycontroller (SCx), a shield time is inserted on the arbitration line(BA), during which the line (BA) is actively driven to “released”.
 5. Amemory system according to claim 4, characterized in that the shieldtime corresponds to the length of one clock cycle of the bus (B).
 6. Amemory system according to claim 1, characterized in that forconsecutive logical memory sector numbers different memory controllers(SCx) are assigned.
 7. A memory system according to claim 1,characterized in that the memory chips (Fx) are flash memories that areerasable in blocks.
 8. A memory system according to claim 1,characterized in that the memory controllers (SCx) are jointly disposedon a semiconductor substrate (H).
 9. A memory system according to claim8, characterized in that the designation of the sequence of the memorycontrollers (SCx) on the bus (B) and of the master (M) takes place bymeans of programming a control register (KR) to the respective memorycontrollers (SCx).
 10. A method for determining the sequence of thememory controllers (SCx) on the bus (B), characterized in that after arepeated designation command by the host system (HS), a memorycontroller (SCx) occupies, after a randomly determined amount of time,the arbitration line (BA) in each case for a specified length of time,provided that no other controller (SCx) has previously reserved the line(BA), from the number of repetitions of this command the controllerderives its controller number (Sx), a confirmation signal is reported tothe host system (HS) in each case, the respective memory controller(SCx) withdraws from the designation process after the confirmation. 11.A method according to claim 10, characterized in that the memorycontroller (SCx) with the controller number 1 is designated as themaster (M).
 12. A method according to claim 10, characterized in thatthe host system (HS) repeats the designation process if insufficientdesignation confirmations are reported.
 13. A method according to claim10, characterized in that the random time for occupying the arbitrationline (BA) is derived from a counter that is subject to componenttolerances.